Phase switching circuit

ABSTRACT

A phase switching circuit utilizing a novel bidirectional transistor having a signal applied to its base and a flip-flop circuit arrangement coupled to its output terminals which may be referred to as either collector or emitter depending upon the operation state of the circuit. The flip-flop circuit has a pair of transistors which act as switches and which are respectively coupled in series with the output terminals of the bidirectional transistor. When each of the flip-flop transistors is conducting, a power supply signal is conducted in opposite directions through the bidirectional transistor depending upon which of the transistors is in the on and which is in the off state. Essentially, the switching action of the flip-flop circuit converts the operation of the bidirectional transistor between emitter follower and collector follower configurations, hence the output signal is shifted from a signal which is in phase with the input signal to a signal which is out of phase with that input signal.

BACKGROUND OF THE INVENTION

1. Description of the Prior Art

Prior phase switching circuits have utilized flip-flop circuits toswitch on and off respective diodes which are in turn coupled to emitterand collector terminals of a standard transistor. The input signal beingswitched is applied to the base of such a transistor and depending uponwhich output diode is in the conducting state, either a signal in phasewith the input signal or a signal which is out of phase with that signalis supplied to an output.

2. Field of the Invention

The field of art to which this invention pertains is phase switchingcircuits and in particular to circuits for switching the phase of aninput signal from a first phase to an opposite polarity by the use of atrigger signal such as a flip-flop signal.

SUMMARY OF THE INVENTION

It is an important feature of the present invention to provide animproved circuit for switching the phase of an input signal from a firstphase to a phase of opposite polarity.

It is another feature of the present invention to accomplish the abovephase switching arrangement with a novel bidirectional and transistor.

It is a principal object of the present invention to provide a novelphase switching circuit which has improved simplicity in circuitconstruction and reduced cost.

It is an additional object of the present invention to provide a phaseswitching circuit arrangement of the type described above using a novelbidirectional transistor and employing first and second switching meansconnected in series with the output terminals of the bidirectionaltransistor for the purpose of switching that transistor between anemitter follower operation state to a collector follower operation statewhereby a phase varying output signal can be obtained in accordance withthe timing of an input trigger signal.

These and other objects, features and advantages of the presentinvention will be understood in greater detail from the followingdescription and associated drawings wherein reference numerals areutilized to designate a preferred embodiment.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 as shows a prior art phase switching arrangement utilizing aflip-flop circuit and a pair of diodes as a means for switching theoperation of a transistor from a first to a second opposing phase.

FIGS. 2 and 3 show detailed drawings of a novel semi-conductor deviceused in the circuit arrangement of the present invention as shown inFIG. 4.

FIG. 4 is a schematic of a phase switching circuit according to thepresent invention utilizing a bidirectional transistor as shown in FIGS.2 and 3 and having the operation of the bidirectional transistorcontrolled by a flip-flop circuit.

FIG. 5a is an equivalent circuit related to FIG. 4 which shows thecollector follower operating state of FIG. 4 as determined by one stateof the flip-flop circuit.

FIG. 5b is an equivalent circuit showing the emitter follower operatingstate of the circuit of FIG. 4 as determined by the opposite state ofthe flip-flop circuit.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

This invention relates generally to phase switching circuits, and moreparticularly to circuits for deriving therefrom a signal, whichcorresponds to an input signal supplied thereto, with the original phaseand with an inverted phase in accordance with a predetermined controlsignal.

A phase switching circuit for obtaining from an input signal an outputsignal which has the original phase and an inverted phase alternatelyfor predetermined repeated durations is required for some purposes. Forexample, in a PAL color television receiver, such a circuit is used as aphase switching circuit for inverting the phase of the chrominancesignal representing an R--Y color difference signal component or a phaseof a reference carrier signal used for demodulating the R--Y colordifference signal component for every other line period and obtainingcontinuously the chrominance signal or the reference carrier signal withthe original phase and the inverted phase alternately every line period.

The present invention provides a phase switching circuit which has anovel and improved circuit arrangement formed with use of a novelsemiconductor device superior in bidirectional conductivity and issuitable for a phase switching circuit used in the chrominance signalcircuit portion of a PAL color television receiver.

The phase control circuit according to the present invention comprisesthe novel semiconductor device acting as a bidirectionally conductivetransistor having an emitter, a base and a collector and supplied withan input signal to one electrode corresponding to the base and aflip-flop circuit provided with a pair of output terminals connected toother two electrodes corresponding to the emitter and collector of thenovel semiconductor device, respectively. The flip-flop circuit isoperated by a control pulse signal to supply an operating D.C. voltagefrom a voltage source to the novel semiconductor device with polarityreversed in a predetermined repetition in accordance with the controlpulse signal. An output signal having the phase identical with the inputsignal and the inverted phase in the predetermined repetition is derivedfrom the electrode corresponding to the emitter or the collector of thenovel semiconductor device.

Referring to FIG. 1, an input transistor 21 has a signal source 15applied to its base and has a pair of diodes 22 and 23 coupled to thecollector and emitter terminals of the transistor, respectively. Anoutput transistor 24 is shown as having its base coupled at a pointbetween the diodes 22 and 23.

A flip-flop circuit 25 has a pair of switching transistors 26 and 27 anda trigger input terminal 28. The flip-flop circuit raises the voltage ofthe anodes of the respective diodes 22 and 23 when the respectivetransistors 27 and 26 are turned off. In this way, an output signalappearing at the base of the transistor 24 is either in phase with theinput signal 15 or out of phase therewith.

Referring to FIGS. 2 and 3, these Figures show a novel semiconductordevice which is used in the invention as described in connection withFIGS. 4, 5a and 5b.

Before describing the present invention, an embodiment of the novelsemiconductor device useable in the invention will be now described.

The emitter-grounded current amplification factor h_(FE) of atransistor, which is one of parameters evaluating the characteristics ofthe bipolar transistor, can be expressed by the following equation (1),if the base-grounded current amplification factor of the transistor istaken as α.

    h.sub.FE = α/1 - α                             1.

the factor α is expressed as follows:

    α= α * β γ                          2.

where α * represents the collector amplification factor, β the basetransfer efficiency and γ the emitter injection efficiency,respectively.

Now, if the emitter injection efficiency γ of an NPN-type is taken intoconsideration, γ is given by the following expression (3). ##EQU1##where J_(n) represents the current density of electrons injected fromthe emitter to the base of the transistor and J_(p) the current densityof holes injected from the base to the emitter of the transistor,respectively.

Since J_(n) and J_(p) are expressed by the following equations (4) and(5), respectively, ##EQU2## the ratio δ of J_(n) and J_(p) is expressedas follows: ##EQU3## where L_(n) represents the diffusion distance ofthe minority carriers in the base of the transistor; L_(p) the diffusiondistance of the minority carriers in the emitter of the transistor;D_(n) the diffusion constant of the minority carriers in the base; D_(p)the diffusion constant of the minority carriers in the base; n_(p) theconcentration of the minority carriers in the base under the equilibriumstate; p_(n) the concentration of the minority carriers in the emitterunder the equilibrium state; V a voltage applied to the emitter junctionof the transistor; k the Boltzmann's constant; T temperature and q theabsolute value of electron charge.

If it is assumed that the impurity concentration in the emitter of thetransistor is taken as N_(D) and that in the base of the transistortaken an N_(A), the term pn/np can be replaced by the term N_(A/N) _(D).Further, since L_(n) is restricted by the base width W and L_(n) = W,the ration γ is expressed as follows: ##EQU4##

The diffusion constants D_(n) and D_(p) are functions of transfer of thecarrier and temperature, and in this case they are assumed constantsubstantially.

As may be obvious from the above respective equations, in order toincrease the current amplification factor h_(FE) of a transistor, it issufficient to make the ratio γ small.

Therefore, in an ordinary transistor, the impurity concentration N_(D)of its emitter is selected high enough so as to make the ratio γ small.

However, if the impurity concentration of the emitter is selectedsufficiently high, for example, more than 10¹⁹ atom/cm³, lattice defectsand dislocation occur in the crystal of the semiconductor body of thetransistor to deteriorate the crystal. Further, due to the fact that theimpurity concentration of the emitter itself is high, a life time τ_(p)of the minority carriers injected to the emitter from the base becomesshort.

Since the diffusion distance L_(p) is expressed by the followingequation (8) ##EQU5## the diffusion distance L_(p) of the minoritycarriers or holes becomes short. Therefore, as may be apparent from theequation (7), δ cannot be made small so much and hence the injectionefficiency γ cannot be made high over a certain value. As a result, thecurrent amplification factor h_(FE) cannot be made high so much in theordinary transistor.

As mentioned previously, the novel semiconductor device useable in thisinvention is free from the defects mentioned just above inherent to theprior art transistor. As the semiconductor device used in thisinvention, an NPN-type one and a PNP-type one could be considered as inthe case of the prior art transistor, but an NPN-type semiconductordevice useable in this invention will be now described with reference toFIGS. 2 and 3, by way of example.

As shown in FIG. 2, the NPN-type semiconductor device consists of afirst semiconductor region 1 of N⁻ type conductivity formed in asemiconductor substrate S of N⁺ type conductivity, a secondsemiconductor region 2 of P type conductivity formed in thesemiconductor substrate S adjacent the first region 1, and a thirdsemiconductor region e of N⁻ type conductivity formed in the substrate Sadjacent the second region 2 to form a first PN-junction J_(E) betweenthe first and second regions 1 and 2 and a second PN-junction J_(c)between the second and third regions 2 and 3, respectively.

With the semiconductor device useable in this invention and shown inFIG. 2, at the position facing the first junction J_(E) and apart fromit by a distance smaller than the diffusion distance L_(p) of theminority carriers or holes injected from the second region 2 to thefirst region 1, a potential barrier having energy higher than that ofthe minority carriers or holes, or at least heat energy is formed in thefirst region 1. In the example of FIG. 2, the impurity concentration inthe first region 1 is selected low sufficiently such as in the order of10¹⁵ atoms/cm³ and region 1a of N⁺ type conductivity or the impurityconcentration of about 10¹⁹ atom/cm³ is formed in the first region 1 toform an LH-junction and hence to form the barrier.

The impurity concentration in the second region 2 is selected in theorder of 10¹⁵ -10¹⁷ atom/cm³ and that in the third region 3 is selectedsufficiently low such as in the order of 10¹⁵ atom/cm³.

In the semiconductor substrate S adjacent to the third region 3 butapart from the second juction J_(c), there is formed a region 3a of N⁺type conductivity and with the impurity concentration of about 10¹⁹atom/cm³.

A first electrode 4E is formed on the high impurity concentration region1a in the region 1 in ohmic contact therewith; a second electrode 4B isformed on the second region 2 in ohmic contact therewith; and a thirdelectrode 4C on the high impurity concentration region 3a adjacent thethird region 3 in ohmic contact therewith, respectively. From theseelectrodes 4E, 4B and 4C there are led out first, second and thirdterminals E, B and C, respectively. In FIG. 2, reference numeral 5indicates an insulating layer made of, for example, SiO₂ and formed onthe surface of the substrate S.

The semiconductor device shown in FIG. 2 can be used as a transistor. Insuch a case, the first region 1 serves as an emitter region; the secondregion 2 as a base region; and the third region 3 as a collector region,respectively, a forward bias is applied to the emitter junction J_(E)and a reverse bias is applied to the collector junction J_(C).

Thus, the holes injected from the base or the second region 2 to theemitter or first region 1 have a long life period of time due to thefact that the emitter region 1 has the low impurity concentration andgood crystal property, and hence the diffusion distance L_(p) of theholes in the emitter region 1 becomes long. As a result, as may beapparent from the equations (6) and (3), the emitter injectionefficiency γ can be made high. However, in the case that the diffusiondistance L_(p) is made long, if the injected holes into the emitterregion 1 may arrive at the surface of the substrate S and may berecombined with electrons on the surface in practice, the diffusiondistance L_(p) could not be made long substantially. With thesemiconductor device shown in FIG. 2, since the potential barrier isformed in the emitter region 1, which potential barrier faces theemitter junction J_(E), at the position with a distance smaller than thediffusion distance L_(p) of the minority carrier, the amount of thesurface-recombination is reduced and the diffusion distance L_(p) can betaken long sufficiently.

Due to the fact that the potential barrier is formed as described abovein the example shown in FIG. 2, there is performed such an effect thatthe current density or component J_(p) of the holes injected from thebase region 2 to the emitter region 1 is reduced. That is, on theLH-junction J_(H) in the emitter region 1, there is caused a false Fermilevel difference or built-in electric field which acts to suppress thediffusion of the holes or the minority carrier. Therefore, if the levelof the Fermi level is sufficiently high, the diffusion current caused bythe concentration gradient of holes and the drift current caused by thebuilt-in electric field are cancelled on the LH-junction with each otherto reduce the hole current J_(p) injected from the base 2 through theemitter region 1 of low impurity concentration. By this effect, theratio of electron current arriving at the collector region 3 relative tocurrent component passing through the emitter junction J_(E) isincreased and hence the emitter injection efficiency γ is increased asapparent from the equation (3) to make the current amplification factorh_(FE) high.

The above level difference (the height of the potential barrier) must bemore than the energy of holes or at least the heat energy. The heatenergy can be approximated as kT but the above level difference isdesired to be more than 0.1 eV. With in the transistion region of thepotential, the diffusion distance L_(p) of the holes must be notterminated within the transition region, or it is required that thediffusion distance L_(p) of the hole must be greater than the width ofthe transition region.

In the case that LH-junction J_(H) is formed as shown in FIG. 2, thepotential barrier of 0.2 eV can be formed by suitably selecting theamount of impurity and gradient of the high impurity concentrationregion 1a.

FIG. 3 shows another example of the semiconductor device useable withthe invention in which reference numerals and letters same as those usedin FIG. 2 indicate the same device so that their description will beomitted.

In the example of FIG. 3, in order to form a PN-junction J_(S) facingthe first or emitter junction J_(E), an additional region 6 of P typeconductivity is formed in the first region 1. In the example of FIG. 3,the distance between the junctions J_(S) and J_(E) is selected smallerthan the diffusion distance L_(p) of the minority carrier in the firstregion 1. The other construction of the example shown in FIG. 3 issubstantially same as that of the example shown in FIG. 2.

With the example of FIG. 3, since the diffusion distance L_(p) of thehole injected to the first region 1 is long as described above, the holearrives at the additional region 6 effectively and then is absorbedthereby. When the additional region 6 is floated from electrical pointof view, its potential is increased as the number of holes arriving atthe additional region 6 is increased. Thus, the PN junction J_(S) formedbetween the regions 6 and 1 is biased forwardly to its rising-up voltagesubstantially, and then holes will be re-injected to the first region 1from the additional region 6. Thus, the concentration of holes in thefirst region 1 near the additional region 6 will be increased, andaccordingly the concentration distribution of holes between thejunctions J_(E) and J_(S) in the first region 1 is made uniform and thegradient thereof becomes gradual to reduce the diffusion current J_(p)from the second region 2 to the first region 1.

In the example of FIG. 3, the additional region 6 which has the sameconductivity type as that of the second region 2 is formed in the firstregion 1 separated from the second region 2, but it may be possible thatthe second region 6 is formed being continuously extended from thesecond region 2.

The above description is made on the case that the first, second andthird regions 1, 2 and 3 of the semiconductor device are operated asemitter, base and collector, respectively. However, in the abovesemiconductor devices the impurity concentrations of the first and thirdregions 1 and 3 surrounding the second region 2 are selected low ofabout equal order and they are arranged symmetrically with respect tothe second region 2, so that if the first, second and third regions 1, 2and 3 are acted as, collector, base and emitter, respectively, thesemiconductor devices can be operated as a transistor reverse in theoperating direction to those mentioned previously.

When the symmetry of the semiconductor devices is utilized, the symmetrycan be emphasized by forming in the third region 3a potential barrierfacing the second junction J_(C), surrounding the same and having theenergy higher than that of the minority carrier or hole in the thirdregion 3 as shown in FIGS. 2 and 3 by dotted lines outside the junctionJ_(C). To this end, the region 3a of high impurity concentration in thethird region 3 is so formed to surround the junction J_(C) and thedistance between the junction J_(C) and the region 3a is selectedsmaller than the diffusion distance of the minority carrier or holeinjected to the third region 3 at the respective parts.

The features of the novel semiconductor devices described above can besummarized as follows which will be apparent from the above description.

1. The current amplification factor h_(FE) is high and can be increasedmore than 3000.

2. The current amplification factor h_(FE) is uniform. That is, with aprior art transistor, the impurity concentration of the emitter regionis selected sufficiently high so as to increase the emitter injectionefficiency or the current amplification factor of the prior arttransistor depends upon the difference of the impurity concentrationsnear the junction between the emitter and base regions, so that it isrequired to select the impurity concentrations in both the regionsrelatively. On the contrary, in the semiconductor devices for use withthe invention, by forming the potential barrier in the emitter region 1facing the emitter junction J_(E), the current component of the minoritycarrier injected in the emitter region 1 is suppressed to increase theemitter injection efficiency, so that the mutual influence between theemitter and base regions 1 and 2 is small due to the fact that theemitter region 1 is selected relatively low in impurity concentration,and the width of the base region 2 and the distribution of impurityconcentration therein can be selected as planned and hence h_(FE) can beuniform as described above.

3. Since the affect by the surface recombination is avoided, the currentamplification factor h_(FE) can be made high even if the current is low.

4. The noise can be reduced. That is, since the main parts of the firstand second junctions J_(E) and J_(C) are formed between the low impurityconcentration regions of P and N conductivity types, crystal defects aresmall. Further, if the impurity concentration near the electrode 4Battached to the second region 2, by way of example, is selected high, acomponent of the emitter-base current, as the transistor, along thesurface of the semiconductor substrate S can be reduced. Therefore, thenoise of 1/f can be reduced. Further, the burst noise and noise of 1/fcan be also reduced by the fact the h_(FE) is high. In addition, if abase expansion resistance γ_(bb) ' is made small, the noise can bereduced even if the impeadance of a signal source is low.

5. The current amplification factor h_(FE) is good in temperaturecharacteristics.

6. The semiconductor devices can be used as bidirectionally conductivetransistors, respectively, and are excellent in symmetry.

7. Since the impurity concentration in the vicinity of the first andsecond junctions J_(E) and J_(C) is low, BV_(BEO) (collector-openedbase-emitter voltage) is high for both the forward and reversedirections of transistors.

8. When the semiconductor devices are used as a power transistor, theirstrength is high because their emission is made uniform by theirdistributed inner resistance in their emitter region.

9. Saturation characteristics are superior.

10. When the region 6, which carrier out injection or re-injection, isformed, the equivalent resistance of the base is made low.

The invention has the basis on the fact that the above novelsemiconductor device has a body structure symmetrical with respect tothe second region 2, and provides a novel circuit which is good inbalance and small in number of elements used therein by employing theabove novel semiconductor device.

Referring to FIG. 4 in connection with FIGS. 5 and 5b, an input signal20 is applied to a base terminal which may be referred to as the secondterminal of a bidirectional transistor 40. Transistor 40 has first andthird terminals which may also be referred as emitter and collectorterminals as shown. A transistor 49 has its base coupled to thecollector terminal of the transistor 40 to receive therefrom the phaseinverted and in phase signals.

A flip-flop circuit 30 has a pair of standard transistors 31 and 32 eachof which can be seen to be coupled in a series path with the emitter andcollector terminals of the bidirectional transistor 40. For instance,the transistor 32 has its emitter and collector coupled through acircuit line which includes the resistor 42, the emitter and collectorof the bidirectional transistor 40, the resistor 41, a resistor 35 to apower supply at point 39. Also, the transistor 31 has its emitter andcollector coupled through a circuit path which includes the resistor 41,the emitter-collector of the bidirectional transistor 40, the resistor42, the resistor 36 and the power supply at point 39. Resistors 43, 44and 45 provide biased for the base of the bidirectional transistor 40.

A pulse trigger signal is applied to an input terminal 33 of theflip-flop circuit to control the operation thereof and hence control therepetition rate at which the input signal 20 is shifted in phase at theoutput which happens to be the collector of the bidirection transistor40.

When the transistor 31 is in the on state, the transistor 32 is off. Byfollowing this circuit this circuit arrangement of FIG. 4, it can beseen that a circuit operation is described as a collector followersystem which is shown in FIG. 5a. Essentially, the collector of thetransistor 40 is connected to a low voltage point which, in this case,is circuit ground through the conducting transistor 31. At the sametime, the power supply is short circuited from being connected to thecollector and is allowed to be connected to the emitter terminal. Hence,in this arrangement as shown in FIG. 5a, the output signal which isapplied to the transistor 49 is in phase opposition to the input signalapplied at the base of the bidirectional transistor.

The opposite is true when the transistor 32 is placed in the conductingstate by the operation of the switching signal applied to the terminal33. This arrangement is shown in FIG. 5b in which the emitter of thebidirectional transistor is essentially connected to circuit groundthrough the conducting state of the transistor 32. This corresponds toan emitter follower configuration which is displayed in FIG. 5b. Theresult is that the signal applied to the base of the transistor 49 is inphase with the signal applied to the base of the bidirectionaltransistor. Hence, according to the triggering operation of theflip-flop circuit, the output signal is either in phase or out of phasewhich is the result desired to be achieved by the present invention.This result is, however, here achieved in a simpler and more directfashion by the use of a single device rather than three devices as is inthe prior art.

I claim as my invention:
 1. A phase switching circuit comprising:abidirectional transistor having first, second and third terminals; afirst circuit path connected to said first terminal; a second circuitpath connected to said third terminal; an output means connected to saidfirst circuit path; a power source having a relatively high voltage;first switching means for switching the first and thirdterminals of saidbidirectional transistor between said power source and a low voltagecircuit point for operation as an emitter follower; said first switchingmeans being connected between a low voltage point and a point on thefirst circuit path; second swiching means for switching the first andthird terminals of said bidirectional transistor between said powersource and low voltage circuit point for operation as a collectorfollower; said second switching means being connected between a lowvoltage point and a point on the second circuit path; means for applyinga time varying signal to said second terminal; and means for applying asignal means to control the sequence of said first and second switchingmeans.
 2. A phase switching circuit in accordance with claim 1, whereinsaid first and second switching circuit comprises a flip-flop circuitand wherein said means for applying a signal means to control thesequence of said first and second switching means comprises means forapplying a trigger signal to said flip-flop circuit.
 3. A phaseswitching circuit in accordance with claim 2, wherein said flip-flopcircuit includes first and second transistors acting as said first andsecond switching means, the collector to emitter circuit of each of saidtransistors forming a series path with the first and third terminals ofsaid bidirectional transistor, each of said switching transistors beingarranged to conduct a signal in opposite directions through saidbidirectional transistor and said switching transistors being connectedto respective circuit branches which serve to supply said power sourceto terminals of said bidirectional transistor for short circuiting saidbranches during the conduction cycle of respective ones of saidswitching transistors.
 4. A phase switching circuit comprising:abidirectional transistor having a first semiconductor region of oneconductivity type; a second semiconductor region of the oppositeconductivity type adjacent said first region with a first semiconductorjunction therebetween; a third semiconductor region of the same type assaid first region adjacent said second region with a secondsemiconductor junction therebetween, said first region being associatedwith a potential barrier having energy higher than that of minoritycarriers injected from the second region to the first region, saidbarrier being provided at a position facing said first junction andspaced from the same by a distance smaller than the diffusion distanceof the minority carriers; first, second and third terminals coupled tosaid first, second and third regions, respectively; a first circuit pathconnected to said first terminal; a second circuit path connected tosaid third terminal; an output means connected to said first circuitpath; a power source having a relatively high voltage; first switchingmeans for switching the first and third terminals of said bidirectionaltransistor between said power source and a low voltage circuit point foroperation as an emitter follower; said first switching means beingconnected between a low voltage point and a point on the first circuitpath; second switching means for switching the first and third terminalsof said bidirectional transistor between said power source and lowvoltage circuit point for operation as a collector follower; said secondswitching means being connected between a low voltage point and a pointon the second circuit path; means for applying a time varying signal tosaid second terminal; and means for applying a signal means to controlthe sequence of said first and second switching means.
 5. A phaseswitching circuit in accordance with claim 4, wherein said first andthird regions of the semiconductor device each have a first portion withan impurity concentration of substantially the same order of magnitudeand said first region is provided therein with a second portion havingan impurity concentration higher than said first portion of the firstregion at a position spaced from said first junction by a distancesmaller than the diffusion distance of the minority carriers toestablish said potential barrier.
 6. A phase switching circuit inaccordance with claim 4, wherein said first and third regions each havea first portion with an impurity concentration of substantially the sameorder of magnitude and an additional semiconductor region of the sametype as said second region is provided in contact with said first regionat a position spaced from said first junction by a distance smaller thanthe diffusion distance of the minority carriers to establish saidpotential barrier.